During the fabrication of memory devices, it is conventional to test the integrated circuits of the memory devices at several stages during the fabrication process. For example, the integrated circuits are normally connected to a tester with a probe card when the integrated circuits are still in wafer form. In a final test occurring after the integrated circuits have been diced from the wafer and packaged, the integrated circuits are placed into sockets on a load board. The load board is then placed on a test head, typically by a robotic handler. The test head makes electrical contact with conductors on the load board, and these conductors are connected to the integrated circuits. The test head is connected through a cable to a high-speed tester so that the tester can apply signals to and receive signals from the integrated circuits.
The testers that are typically connected to test heads may assume a variety of forms. They are generally relatively large, complex, and expensive standalone test units, and, in some cases, may be connected to several test heads to simultaneously test the memory devices on several load boards. The testers normally function to write known data to the memory devices mounted on the load boards, and then read data from the memory device and compare the read data to the known data. If all of the comparisons are positive, the memory devices are assumed to be functioning properly. Timing tolerances of the memory devices may be tested by varying the timing relationships between various signals, such as data signals and data strobe signals that are used by the memory devices to capture write data and by the tester to capture read data.
In the past, the data written to the memory devices have often been in a regular pattern of “1s” and “0s” such as a “checker board” pattern that stores all binary values in an array of memory cells adjacent memory cells storing the complementary binary value. Although testers that cause this pattern of data to be stored in memory devices have the advantage of being very capable of detecting memory cell leakage problems, the use of a fixed pattern of data can cause other types of errors to go undetected. The primary reason why errors that may occur during use go undetected is that the regular pattern of data stored in the array of memory cells does not accurately simulate patterns of data that are stored in the memory array during use. To address this issue, conventional memory device testers may generate a pattern of data using an algorithmic pattern generator, which may generate data this is pseudo-random in nature. The storage of pseudo-random data more closely approximates the data that will actually be stored in a memory device during use, and it therefore allows manufacturing defects to be detected that might go undiscovered if a regular pattern of data were stored in the memory device.
Unfortunately, conventional testers that may use an algorithmic pattern generator generate data only in conjunction with conventional memory commands and memory addresses of the type received by dynamic random access memory devices, static random access memory devices, flash memory devices, etc. More recently, memory devices have been proposed and are now being introduced that receive packets through a high-speed communications link that may have one or more serial lanes. Such packets generally include command bits, address bits and write data bits. Further, the memory devices to which the packets are applied may respond with read data in the form of packets containing read data bits. Unfortunately, testers that can generate and insert in the packets an algorithmically generated pattern of data have not been developed. Therefore, the benefits of being able to store data generated by an algorithm pattern generator is not available to testers for testing packetized memory devices.
There is therefore a need for a packetized memory device tester and method that can store algorithmically generated patterns of data in packetized memory devices, and then read data packets from the memory devices to determine if the pattern of read data matches the pattern of write data.